1. Technical Field
The present invention relates generally to a semiconductor circuit, and more particularly to a semiconductor memory apparatus.
2. Related Art
FIG. 1 is a diagram illustrating the structure of a known semiconductor memory apparatus.
Referring to FIG. 1, the semiconductor memory apparatus has a wide input/output (IO) architecture capable of performing a data input/output operation at high speed with an increased data bandwidth.
The semiconductor memory apparatus includes a plurality of memory blocks 10, 20, . . . , 40 arranged in a two-dimensional manner, and a wide IO line (not illustrated) is formed between the respective memory blocks 10, 20, . . . , 40. That is, the semiconductor memory apparatus inputs and outputs data using a large data bandwidth.
Among the plurality of memory blocks 10, 20, . . . , 40, the first memory block 10 will be representatively described in detail as follows. The first memory block 10 includes a plurality of memory banks BANK0 to BANK3. Each of the memory banks includes a plurality of memory cells arranged in a two dimensional manner. A row control area includes a circuit for controlling a row path of each memory bank, and a column control area includes a circuit for controlling a column path of each memory bank.
A peripheral circuit area includes a command processing circuit, a power supply circuit, an input/output circuit and the like, in order to control the operations of the memory blocks 10, 20, . . . , 40.
When the operation of a specific memory block among the plurality of memory blocks 10, 20, . . . , 40 is repetitively performed, the temperature of a spot where the operation of the memory block is repetitively performed may excessively increase in comparison with other spots. Hereafter, a spot where the operation of a specific memory block is repetitively performed or the temperature is increased by heat transferred from outside will be referred to as ‘hot spot’.
A semiconductor memory apparatus consisting of memory cells for storing data through electric charges of capacitors should perform a refresh operation at each predetermined cycle, in order to maintain the data stored in the memory cells. As the temperature increases, the time during which the data stored in the memory cells are maintained decreases. Therefore, the refresh operation cycle should be set to become shorter with the increase in temperature.
The semiconductor memory apparatus of FIG. 1 includes a temperature compensated self refresh circuit (TCSR) 50. The TCSR 50 is configured to control the refresh operation cycle based on temperature sensed by a temperature sensor T_SENSOR included therein.
As illustrated in FIG. 1, however, when a hot spot occurs in the third memory bank BANK2 of the second memory block 20, the TCSR 50 does not accurately reflect the temperature increase of the hot spot in controlling the refresh operation cycle, because the hot spot and the TCSR 50 are separated at a large distance from each other. Therefore, the reliability of data stored in memory cells adjacent to the hot spot may decrease.